In the past, conventional computer architectures utilized a sequential program execution model, whereby an architectural program counter sequenced instructions in a FIFO (first-in-first-out) scheme. In other words, a current instruction would be completed prior to beginning the next instruction. However, as computer processing speed became an important issue, computer architectures began using pipelined execution models. A pipelined data processor permits several instructions to be transmitted to the processor simultaneously or in an overlapping manner.
However, the use of a sequential model and a pipelined model may conflict with one another. For example, a pipelined instruction may modify the process state in a different order than that defined by the sequential model. When such a conflict occurs, a so-called "interrupt" has taken place. In short, an interrupt is an event that changes the normal flow of program execution. Typically, when an interrupt occurs, the processor briefly stops the currently executing process to tend to the interrupt. Once the interrupt is handled (often by an interrupt handler, such as a software application), the original process continues by retrieving state information regarding the interrupt process that has been saved. Such information that is saved includes program counter information that defines which instructions of the interrupted process have completed execution.
In regard to the pipelining process of a processor, it can generally be divided into five stages: instruction fetch (IF), instruction decode and operand fetch (DI), instruction execution (EX), memory access (MA) and write back (WB). If some instructions require multiple sub-instructions or "microinstructions" to implement, then a microinstruction sequencer is required. An instruction composed of one or more limited number of microinstructions is called a "macroinstruction." For example, when a macroinstruction I.sub.i is read from the instruction fetch stage, it is decoded into microinstructions I.sub.i,1, . . . , I.sub.i,z (where z is an integer, and z.gtoreq.1) by the microinstruction sequencer at the DI stage before it continues to the subsequent stages. When an internal exception (an interrupt that is caused by an instruction) or an external interrupt (an interrupt not caused by a specific instruction but by external sources) occurs, there are several conventional methods to ensure a "precise interrupt." However, such conventional methods have several shortcomings, as will be described below.
A precise interrupt, as opposed to imprecise, are utilized to essentially guarantee that the original process continues after the interrupt is handled (assuming that such interrupt in non-catastrophic). According to the definition of a precise interrupt in "Implementing Precise Interrupts in Pipelined Processors" of James E. Smith et al. (IEEE Trans. on Computers, Vol. 32, No. 5, May 1988), an interrupt is precise if the following criteria are met:
1. All instructions, before the instruction indicated by the program counter, have completed execution and have modified the process state (information relevant to a process) correctly, PA1 2. All instructions, after the instruction indicated by the program counter, have yet to execute and have not modified the process state, and PA1 3. The program counter information points to an instruction (that caused the interrupt) that is completely executed or completely non-executed.
For example, according to the definition of a precise interrupt in "Implementing Precise Interrupts in Pipelined Processors" of James E. Smith et al. (IEEE Trans. on Computers, Vol. 32, No. 5, May 1988), when an exception or interrupt occurs, instructions before interrupt instruction I.sub.i of the program counter (PC) are stored by the system and must be completed. Thereafter, the subsequent instructions must be discarded. Furthermore, the state of the system must be recovered to that of a completed instruction before I.sub.i or that of the completed I.sub.i.
The above notwithstanding, for some macroinstructions, there are certain points existing between its microinstructions. When an exception or an interrupt occurs at these points, it is still possible to define the state of the system, such that the exception or the interrupt can be processed at these points, called segmented points, and a precise interrupt may be maintained. For example, REP MOVS M1 M2 is a repetitive instruction, which uses a counter for repetition. It repeatedly executes the memory move instructions (MOVS M1 M2) to move the data referred to by M1 to the memory position referred to by M2 until the counter reaches a defined value and the next macroinstruction is executed. When an interrupt or an exception is processed between memory moves, the program counter (PC) value of the macroinstruction is stored and the interrupt service routine is executed. At this point in time, the system is in the state of having finished the memory move, and the counter maintains the number of moves to be repeated. When the interrupt service routine is executed to its completion, the same macroinstruction will re-execute to continue with the memory moves that are to be repeated in accordance with the counter. In fact, in this particular example, the interrupt and the exception between the memory moves can be processed without affecting the precise interrupt. Thus, the segmented points are positioned between the memory moves while maintaining the precise interrupt.
For a pipelined data processor with a sequencer, when the macroinstruction is translated into multiple microinstructions, a non-microinstruction pipelined data processing method will be used if there is no option available for processing the microinstruction. When an interrupt or an exception occurs, the macroinstruction I.sub.i is translated into multiple microinstructions I.sub.i,1 -I.sub.i,z. Assumably, if some of the microinstructions have already changed the state of the system, it is necessary to let I.sub.i be executed to its completion in order to maintain the precise interrupt. In other words, the interrupt must be processed after I.sub.i. The system stores the PC value of the next instruction I.sub.i+1 and maintains the state of the completed I.sub.i. This is shown in FIG. 1, where I.sub.i-1, I.sub.i, I.sub.i+1, I.sub.i+2, I.sub.i+3, I.sub.i+4, and I.sub.i+5 are macroinstructions, I.sub.i has been translated into four microinstructions I.sub.i,1 -I.sub.i,4, and the remaining macroinstructions are translated into a single microinstruction. I.sub.i is decoded at the DI stage to become I.sub.i,1 -I.sub.i,4. When an external interrupt occurs at T.sub.7, the system must delay the processing of this external interrupt until T.sub.10, i.e., after microinstruction I.sub.i,4 has completed the WB stage, in order to ensure that the system is in the state of the completed I.sub.i when the interrupt occurs. With this method, however, it is impossible to process an interrupt or an exception in real time. The situation further deteriorates if the macroinstruction is composed of a long string of microinstructions.
It is therefore an object of the present invention to overcome the disadvantages of the prior art by providing a pipelined data processor that utilizes two control bits to accelerate the reaction time to interrupts, while maintaining a precise interrupt.